1. Field of the Invention
The present invention relates to a method for fabricating semiconductor devices, and more particularly to a method for fabricating a self-aligned contact hole suitable for dynamic random access memory cells (DRAM).
2. Description of the Prior Art
Referring to FIGS. 1A through 1I, the cross-sectional side views of a conventional method for fabricating a self-aligned contact hole are depicted in sequence.
Referring now to FIG. 1A, a cross-sectional view of the first step is schematically shown. In FIG. 1A, a polysilicon layer 14, a polycide layer 16, a silicon nitride 18, and a silicon oxide 20 are sequentially formed by chemical vapor deposition on a silicon substrate 10 having a conductive region 12, for example a source/drain region. The silicon nitride layer 18 has a thickness of approximately 2000 Angstroms, and the silicon oxide layer 20 has a thickness of approximately 500 Angstroms.
Next, as shown in FIG. 1B, the silicon oxide layer 20 and silicon nitride layer 18 are etched to expose the upper surface of the polycide layer 16.
Then, as shown in FIGS. 1B and 1C, using the remainder silicon oxide layer 20 and the silicon nitride layer 18 as the etching mask, the polycide layer 16 and the polysilicon layer 14 are etched by anisotropic etching to form a trench 21 which exposes the conductive region 12.
Referring now to FIG. 1D, a silicon nitride layer 22 is deposited on the bottom and sidewall of the trench 21 by chemical vapor deposition.
As shown in FIG. 1E, the silicon nitride layer 22 is etched back to form a first nitride spacer 22a thereby exposing the conductive region 12. At the same time, the silicon oxide layer 20 is removed.
Referring now to FIG. 1F, a borophosphosilicate glass (BPSG) layer 24 is filled into the trench 21, extending the upper surface of the silicon nitride layer 18. Then, a photoresist layer 26 is formed in a predetermined position by using photolithography process.
Next, as shown in FIGS. 1F and 1G, a part of the BPSG layer filled in the trench 21 is removed using the photoresist layer 26 as the etching mask, thereby forming a self-aligned contact hole 27 which exposes the conductive region 12. Afterward, the photoresist layer 26 is removed. In order to completely expose the conductive region 12, a part of the first nitride spacer 22a and the silicon nitride layer 18 would be removed too.
Afterwards, referring to FIGS. 1G and 1I, a silicon nitride layer 28 is formed by chemical vapor deposition. Then, the silicon nitride layer 28 is etched back to form a second nitride spacer 28a, thereby achieving a better insulating effect.
However, the conventional self-aligned contact hole process suffers from problems. For example, the narrow slit of trench 21 containing first nitride spacer 22a can cause the etching step of silicon nitride layer 28 to stop (as shown in FIGS. 1H and 1I).
Moreover, in order to serve as the etching stop layer, the silicon nitride layer 28 must have a larger thickness, for example 2000 Angstroms. Therefore, the thermal budget will be increased.